When designing a cryptographic solution, a simple rule of thumb often arises: hardware
is faster and more secure than software. However, such a statement is too broad. Hardware and software
possess different characteristics and optimization potential, as well as differing costs regarding modification, maintenance,
and protection. Therefore, comparing a single throughput figure is insufficient for making a decision.
One must also consider latency, determinism, resource consumption, updateability, costs, resilience against
errors and attacks, error and attack detection capabilities, and—above all—the requirements of the specific application.
Moreover, the boundary between hardware and software is blurring in practice. Software can utilize
processor instructions designed for cryptography, a specialized accelerator, or other hardware resources.
Conversely, programmable hardware may incorporate relatively general-purpose logic. It is therefore more meaningful
to compare specific architectures rather than the abstract categories of "hardware" and "software."
Differences exist between hardware and software implementations of cryptographic algorithms
regarding performance, latency, cost, updateability, error detection methods, and security
features. However, without specific measurements, it is impossible to reliably determine which variant
is more suitable for a given system.
Furthermore, manufacturers may not disclose all the parameters necessary for a true assessment. The nominal
throughput of a cryptographic accelerator does not necessarily correspond to the throughput of the entire system.
The result can be influenced by memory-to-accelerator transfers, request queues,
synchronization, the network interface, the operating system, or resource sharing among multiple applications.
| Area | Hardware | Software |
| Performance | Determined by architecture, data path width, number of parallel blocks, clock cycles per operation, frequency, and technology. With ASICs, optimization can be tailored directly to the required algorithm. | Depends on the processor, its architecture, frequency, number of cores, available instruction set extensions, and implementation quality. The compiler and the cryptographic library used also play significant roles. |
| Latency | Can be predicted quite accurately with a suitable architecture. Depends, for example, on the number of clock cycles, the critical path, and the pipeline. | Influenced not only by the number of instructions but also by cache, interrupts, thread scheduling, memory access, and the operating system. |
| Throughput | Can be increased through parallelism, wider data paths, pipelining, and multiple instances of the cryptographic core. | Depends on CPU performance and available parallelism. Can be increased using multiple cores, SIMD, or hardware cryptographic instructions. |
| Resources | For ASICs and FPGAs, this relates primarily to logic, memory, registers, I/O, and manufacturing technology. For FPGAs, resources such as LUTs, FFs, BRAM, and DSPs can be monitored. | Primarily consumes CPU and memory resources, and potentially a cryptographic accelerator. |
| Power consumption | Specialized hardware can be highly energy-efficient per processed bit or block. | Depends on processor load and the time required for cryptographic processing. |
| Cost | Commodity acceleration may incur low additional costs. Conversely, a specialized ASIC entails high initial costs for design, verification, and manufacturing. | Does not require designing a new chip but involves costs for development, integration, testing, maintenance, and the platform itself. |
| Flexibility | ASICs are limited; FPGAs and programmable hardware offer greater flexibility. | Typically high. The algorithm or its implementation can be modified via updates. |
| Vulnerability remediation | Fixing a fixed-function ASIC can be extremely costly or practically impossible. The situation is better with FPGAs and updatable firmware. | Fixes can usually be distributed via updates, provided the platform and update mechanism allow it. |
| Error detection | Redundancy, parity checks, monitoring mechanisms, or fault-injection protections can be implemented. | Validation, integrity checks, and other mechanisms can be implemented, though the outcome is also influenced by the processor, memory, and operating system. |
| Side-channel protections | Can be designed directly into the circuitry—for example, masking or hiding techniques. These protections can increase area and power consumption. | Constant-time execution and other techniques can be used, but implementation depends on the specific processor, cache, and memory subsystem. |
| Determinism | Typically high, provided the architecture is designed with a predictable cycle count and data path. | Usually lower in a standard multitasking system. Bare-metal or real-time environments can be significantly more deterministic. |
| Support period | Depends on component availability and the design lifecycle. | Depends on the operating system, libraries, firmware, and the platform manufacturer. |
| Verification and certification | May include RTL verification, physical implementation, and testing against fault or side-channel attacks. | Includes source code, libraries, APIs, dependencies, and the specific runtime environment. Updates may require re-testing. |
| Scalability | Performance can be increased via parallel cores, pipelining, or wider data paths, at the cost of area and power consumption. | Faster CPUs, more cores, or accelerators can be utilized. |
| Algorithm lifecycle | A fixed ASIC may require new hardware if the algorithm changes. | The algorithm can usually be modified or updated via software. |
The table does not indicate a universal winner. The choice of architecture must be based on the required combination of performance, latency, security, flexibility, and lifecycle.
Throughput indicates the amount of data an implementation can process per unit
of time. Latency, on the other hand, represents the time from the generation of a request or data block to the moment
the result becomes available. These metrics are not interchangeable. A parallelized implementation
can achieve very high aggregate throughput, yet an individual request may still
require a relatively long time due to computation initialization, synchronization, memory
access, waiting for the accelerator, or the completion of subsequent operations.
With symmetric algorithms, hardware acceleration enables high throughput,
especially when processing large blocks or multiple parallel streams. Operations based
on public keys, key exchange, digital signatures, or signature verification have a different
computational nature, and their latency can be more significant. Therefore, when evaluating
performance, it is insufficient to look merely at clock frequency or the nominal number of cryptographic operations.
The result is influenced by factors such as:
In the case of software, additional factors come into play—such as the operating system, thread scheduling, context switching, virtualization, and other mechanisms—which can introduce a variable component to latency. From a security perspective, it is therefore advisable to monitor not only the average operation time but also the variance and, for instance, the upper quantiles of latency. A system with a very short average operation time may be unsuitable for time-critical applications if, under certain circumstances, it exhibits a significantly longer response time.
When designing a specialized cryptographic datapath, performance can be scaled by adjusting the datapath width. However, the following values should be viewed as an illustrative example rather than a universal benchmark for a specific ASIC.
| Datapath | Gate equivalents | AES-128 clock cycles |
| 8-bit | 5,052 GE | 160 |
| 16-bit | 6,281 GE | 80 |
| 32-bit | 7,155 GE | 40 |
| 64-bit | 11,628 GE | 20 |
| 128-bit | 20,410 GE | 10 |
The table shows that a wider datapath can reduce the number of clock cycles required to process a block. At the same time, however, implementation complexity increases, and overall system latency cannot be directly inferred from these figures alone. For instance, if we consider a model accelerator operating at 1 GHz, the given clock cycle counts yield approximately the following values:
| Datapath | Model throughput | Model AES-128 latency |
| 8-bit | 0.8 Gbps | 160 ns |
| 16-bit | 1.6 Gbps | 80 ns |
| 32-bit | 3.2 Gbps | 40 ns |
| 64-bit | 6.4 Gbps | 20 ns |
| 128-bit | 12.8 Gbps | 10 ns |
These values describe only the cryptographic operation itself within the given model. They do not include data transmission, queuing, memory access, synchronization, or other system components. Therefore, they should not be confused with end-to-end latency.
In remote control or data processing scenarios, the entire chain must be considered. When data is transmitted between devices, cryptographic protection can be applied either before transmission or after data reception. In remote decision-making, a similar process occurs in the reverse direction as well. A model example might look like this:
In the model described, the total delay amounts to approximately 11 µs. If data
preparation and cryptographic operations take about 1 µs, they already account for a
significant portion of the time budget. This can be critical, for instance, in power
electronics and converters, RF/DSP control, ultrasonic sensing, protection and
switching functions, or certain optical and telecommunication systems. However,
these are not the only examples; the same principle applies wherever there is a
fixed time budget and cryptographic protection consumes a significant share of it.
Importantly, in such a situation, the choice between hardware and software may not
be the primary issue. If the entire system is too slow, merely optimizing the
cryptographic operation might not solve the problem. The entire timing chain
must be evaluated.
For systems dealing with very fast or rapidly changing processes, determinism
also becomes significant. It is not merely a question of whether a cryptographic mechanism completes an operation
sufficiently fast on average, but whether it can be assumed with sufficient certainty
that it will complete it within the required time interval. Each additional step between
obtaining information and the system's reaction introduces its own latency and
potentially jitter—that is, temporal uncertainty. Overall response time can be
simplified as the sum of latencies associated with sensing, preprocessing,
cryptographic operations, communication, synchronization, decision logic, and
physical reaction.
For time-critical systems, a mechanism with predictable and bounded latency may
therefore be preferable to a solution offering higher average performance but
significantly variable response times. This marks a key distinction between a
standard information system and a control system. In a standard system, a few
milliseconds of additional latency might be negligible. In a process with a very
short time horizon, however, the same latency could render the information
useless before it is even verified.
Thus, cryptographic protection can simultaneously enhance security—in terms of
confidentiality and integrity—and consume a portion of the system's time budget.
This is not an argument against cryptography; rather, it is a reason to evaluate
it as an integral part of the entire system.
This issue is also related to classification. The value of information is not
necessarily constant over time. Certain information holds high value only
before or during a specific event. Others may hold long-term value for analysis, planning, or reverse-engineering
system characteristics.
A single data point may become practically insignificant after a certain time,
but a large volume of similar data can enable the retrospective derivation
of process characteristics, measurement accuracy, response times, design
features, or other system parameters. Consequently, the temporal degradation
of information value is not necessarily monotonic. Immediate value may drop
sharply, while analytical or evidentiary value may persist. Therefore, when
assessing protection needs, it is appropriate to consider:
This gives rise to the concept of an information time budget. If we designate
the moment of information creation as t0 and the latest moment by
which effective action can be taken based on it as tD,
then the available time budget can be approximately expressed as:
TD = tD - t0
This interval must accommodate not only the cryptographic operation but the
entire processing and response chain. In practice, therefore, the following
condition is insufficient:
T(crypto) < TD;
it is more important to ensure T(end-to-end) < TD;
at the same time, it is advisable to leave a margin for jitter, packet loss, retransmissions,
load fluctuations, and other unforeseen conditions.
If this condition is not met, the cryptographic mechanism—even if technically
implemented correctly—may fail to provide practical protection for the required operation,
because the protected information becomes available only after the point when it can
effectively be used. In such cases, the entire system architecture must be evaluated:
whether certain calculations can be performed in advance, whether operations can be parallelized,
whether the time-critical data path can be separated from less critical logging,
or whether a different cryptographic context with lower overhead can be used.
Therefore, it is not appropriate to evaluate cryptography solely based on the number of bits processed per second.
Latency, latency variance, determinism, and overall end-to-end response time are equally
important for system design. Hardware can offer high and predictable throughput, but
at the cost of greater specialization or more difficult to update. Software offers greater flexibility,
but its latency can be affected by other system layers. Moreover, in practice,
hybrid solutions often emerge, meaning the boundary between the two approaches is not sharply defined.
Therefore, the decisive factor is not whether hardware or software is generally faster.
What matters is whether a specific architecture meets the application's timing constraints
at the required security level while simultaneously providing sufficient headroom for both
normal and exceptional operating conditions. As with classification, the temporal
dimension of the information must be taken into account. Information may be critical
only for a short period, yet it may also possess long-term analytical or evidentiary value.
Consequently, cryptographic protection requirements should not be determined solely
by data volume or immediate sensitivity, but also by when the information requires
protection, how long that protection must last, and when the information must remain usable.
This shifts the focus from the performance of cryptographic operations themselves
to the roles and functions of the various components within the cryptographic infrastructure. Other
part of the series will therefore focus on the roles used and their relationship to key management
material.
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